In this section electronics projects that were developed are displayed here click on the links next to the description to connect to the appropriate report. In the first year- of the modules were completed with Electronics workbench, this was then changed to the Max Plus II electronics CAD design in the second and third year.
Analogue Circuit Analysis
In this assignment analysis of various dc and ac circuits was required. After accomplishing this confirmation of these results were checked using through the electronics CAD package of EWB.
Seven Segments Display
This project was to design part of a decoder for a seven-segment display. There was a requirement that the input is to be a three bit binary number (A,B,C). The inputs zero to five should be catered for with the correct decoder for driving lights 'c' and 'e' are required.
To design a sequence generator with a control line Z, with the control line 'high' pattern flows in one direction and then reverses when the control line is 'low'. The system is designed using EWB and was created using T-type flip flops..
To design a sequence generator with a control line X, System using both VHDL and AHDL versions and comparison of advantages and disadvantages made.
To design and implement a traffic light design system using formal design methodologies and VHDL and AHDL in the development process. With the addition of a push button switch to temporarily pause the systems operation.
To extend the implementation to include an extra element in this case I decided to incorporate an pedestrian crossing scenario into the circuit.
To design a regular repeatable system for a 5x5 systolic array multiplier which takes two five integers and generates the product in parallel. I estimated the time delay of the circuit and then compared results of actual simulation results. Then I produced a suitable architecture for a fixed point serial multiplier with X as 5 bits and Y as 6 bits. A comparison of these circuits was then made to monitor the respective advantages and disadvantages of the circuits.
To design a suitable hardware architecture for the finite impulse response filter with X(t) as a sampled value of a 5 bit input data at time t. Secondly to suggest an alternative hardware architecture for a FIR filter and then compare and contrast with the first filter. Then thirdly comment on the important aspects of hardware implantation of an FIR filter with variable filter coefficients using floating-point arithmetic's.
The formal design and implementation of a controller for a programmable digital combination lock on a safe. The implementation will be based on a dynamic PLA with a two-phase clocking strategy.
A discussion on the various components that can be used with the construction of various power electronic circuits.